The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods for providing improved structures in which gate-to-local interconnect capacitance is reduced by utilization of a low dielectric constant material for a local interconnect etch stop layer, namely silicon carbide (xe2x80x9cSiCxe2x80x9d).
Integrated circuit designs have numerous active devices such as transistors laid out on a common substrate, typically silicon. A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of active devices and circuit features.
In order to achieve higher device density, smaller geometry devices have been developed. Isolation regions separate the active devices to prevent electrical interference between them. Such isolation regions may be formed early in the fabrication process by masking the intended active regions and growing an insulator, such as an oxide, in the non-masked isolation regions. The grown oxide, referred to as a field oxide, serves to isolate and define the active regions. The active devices are formed by various processing steps and then covered with an insulator.
In order to interconnect the various active devices, one or more overlying metalization layers are formed on top of the insulator with connections to the devices provided by conductively filled openings in the insulator. The various devices are thereby interconnected between adjacent active devices that may be disposed underneath the insulating layer. Such an interconnection, known as a local interconnect (xe2x80x9cLIxe2x80x9d), is formed on top of the isolating field oxide and prior to forming overlying insulating and metalization layers.
A local interconnect formed between two active regions will typically connect a source/drain region of one active region to the source/drain region of the other. However, local interconnects may also be formed between polysilicon gate regions and between a polysilicon gate region and source/drain region. In general, local interconnects are used to connect electrodes of active devices within an integrated circuit to provide an electrical connection between two or more conducting or semi-conducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logic circuit using a local interconnect.
Local interconnects typically comprise a relatively low-resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), titanium/titanium nitride or a like conductor metal, which is deposited within an etched opening, such as a via or trench that connects the selected regions together. The use of local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit""s performance.
As circuit density increases, the demand for more efficient, effective and precise processes for forming smaller local interconnects increases and, as devices scale, the increased capacitance between gate/poly (gate/polysilicon) features and tungsten or copper damascene local interconnect features becomes significant. These narrow spaces are frequently filled with a high dielectric constant material, such as SiN or SiON. As such, it has been found difficult to provide low RC (resistance capacitance) interconnection patterns, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization. Accordingly, there is need to reduce the composite dielectric constant of the materials between polysilicon/Local Interconnect (xe2x80x9cpoly-LIxe2x80x9d).
The small spaces between gate and LI are typically filled with a dielectric material such as SiON or SiN having a dielectric constant K of about 5 to about 7. SiN or SiON is used as an LI etch stop layer to protect the field oxide and poly during LI etch. It would be advantageous if the composite K between gate-LI is lowered to a range of about 3 to about 5.5, preferably about 3.7 to about 4.7. Lower-K materials provide less capacitance, increasing the propagation speed of electrical signals. Thus, the use of lower K materials would provide a semiconductor chip with an overall lower RC delay and an improved operating speed relative to prior designs.
The above and other needs are met by the present invention which provides methods for substantially reducing the composite K of the materials between poly-LI. In an embodiment, the method includes:
forming a field dielectric region on a substrate isolating an active region;
forming a first transistor in the active region, the transistor comprising a first gate electrode over the substrate with a gate dielectric layer therebetween and source/drain regions in the substrate on opposite sides of a channel region under the gate electrode;
forming a second transistor having a second gate electrode extending on the field dielectric region;
depositing a conformal layer comprising silicon carbide (SiC) over the first and second gate electrodes, substrate surface and field dielectric region;
depositing an inter-dielectric layer (a.k.a. inter-layer dielectric) over the SiC layer;
etching an opening through the inter-dielectric layer stopping on and exposing a portion of the SiC layer;
etching the exposed portions of the SiC layer to extend the opening and to expose a portion of the source/drain region of the first transistor, the second gate electrode and the field dielectric region; and
filling the extended opening with a conductive material to form a local interconnect between the exposed source/drain region and the second gate electrode.
Embodiments include depositing a dielectric layer of silicon carbide (xe2x80x9cSiCxe2x80x9d) by Plasma Enhanced Chemical Vapor Deposition (PECVD) or High-Density Plasma (HDP) techniques as an etch stop layer in place of SiN or SiON. The inter-dielectric layer may comprise any suitable dielectric material, such as a TEOS oxide.
Another aspect of the present invention is a semiconductor device comprising a SiC dielectric stop layer, which semiconductor device can be made according to the above methods. In particular, the semiconductor wafer or device comprises:
a substrate having a main surface;
a field dielectric region isolating an active region;
a transistor formed in the active region, the transistor comprising:
a first gate electrode on the main surface of the substrate with a gate dielectric layer therebetween; and
source/drain regions in the substrate with a channel region therebetween underlying the gate electrode;
a second gate electrode extending on the field dielectric region;
a conformal layer of silicon carbide (SiC) over the transistor, second gate electrode and field dielectric region;
an inter-dielectric layer on the SiC layer;
an opening formed in the inter-dielectric layer and SiC layer exposing a portion of a source/drain region, field oxide region and second transistor; and
conductive material filling the opening and forming a local interconnect between the source/drain region of the transistor and second gate electrode.
The foregoing and other features, aspects and advantages of the present invention will become more apparent to the skilled artisan from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.